A phase-locked loop, commonly referred to as a PLL, is a control loop that generates an output signal whose phase is related to the phase of an input, or reference, signal. A PLL typically has a local oscillator with a variable frequency and a phase detector. The local oscillator generates a periodic signal; the phase detector compares the phase of that signal with the phase of a reference input periodic signal and adjusts the oscillator to keep the phases matched. The output signal is brought back for comparison with the input signal in a feedback loop.
Keeping the phases of the input and output signals in lockstep also implies keeping the frequencies of the input and output signals the same, or in a fixed relationship. Thus, in addition to synchronizing the signals, in a PLL the output frequency can track the input frequency or it can be a frequency that is a multiple of the input frequency.
These properties allow PLLs to be widely used in such applications as radio, telecommunications, computers, and others. PLLs can be used to demodulate a signal, recover a signal from a noisy communications channel, generate a stable frequency that is a multiple of an input frequency (frequency synthesis), or synchronize clocks and distribute precisely timed pulses in digital logic circuits such as microprocessors. Since a building block containing a complete PLL may be easily inserted in an integrated circuit, such techniques are widely used in modern electronic devices, with output frequencies from a fraction of hertz (Hz) up to many gigahertz (GHz).
One way of obtaining a local oscillator signal, and thus an output signal, that is proportional to the input signal is well known in the art. Digital dividers are inserted in the reference path and/or the feedback path of the PLL, and their relationship determines the relative frequencies of the signals.
In such a known method, the frequency of an input reference signal FREF is divided, by an integer N, by the use of a digital divider, to create a signal at a frequency FREF/N. Similarly, the output frequency FLO of the local oscillator is divided by an integer M to create a signal at a frequency FLO/M.
These two frequencies are fed to the phase detector, which is constructed to adjust the frequency of the local oscillator such that:
            F      REF        N    =            F      LO        M  which means that the frequency of the local oscillator is given by:
      F    LO    =            F      REF        ⁢          M      N      Consequently, such a PLL can generate any frequency relative to the input reference frequency that is defined by the ratio of two integers M/N.
A typical prior art PLL using this principle is shown in FIG. 1. PLL 100 contains a local oscillator 102, a phase detector 104, digital dividers 106 and 108, and a filter 110. An input signal having a frequency of FRET is applied to a digital divider 108 and the frequency FREF is divided by an integer N. The resulting frequency FREF/N is then applied to the phase detector 104. This drives the local oscillator 102 (which is often a voltage controlled oscillator) to a frequency FLO, which is the output frequency. The signal from the local oscillator is also fed back through the other digital divider 106 where its frequency is divided by M, so that phase detector 104 also receives the frequency FLO/M. The phase detector causes the relationship between FLO and FREF to be as described above, and results in the value of Flo in the equation above.
Filter 110 is located between phase detector 104 and local oscillator 102, and is typically a filter of a second order or higher. One of skill in the art of PLLs will appreciate that many variations on filter 110 are known and may provide benefits such as noise reduction, stability, etc.
It will be apparent to those of skill in the art that in such a PLL the most efficient operation takes place when N=1. This allows signals to arrive at the phase detector at the fastest rate possible for a particular input signal (i.e., the same frequency as the input signal since FREF/1=FREF), which allows for phase detector “events” (i.e., comparisons) and thus adjustments to the local oscillator to occur at the same rate, minimizing the time between adjustments during which differences may accumulate in the phase of the local oscillator compared to the input signal. However, this situation is not common, since if N=1 the value of FLO is limited to integral multiples of FREF.
It is also known in the art of PLL design that the need to find values of M and N which convert both FLO and FREF to a common frequency to apply to the phase detector causes a problem to arise when M and N are large numbers that have no common factors (M and N are said to be “largely relatively prime” in this case). Consider the situation if a frequency is desired of 500/91 times 27 megahertz (MHz), something often required in multimedia chips. Using a traditional PLL as in FIG. 1 above, M=500 and N=91, with an input frequency of 27 MHz. The values of M and N cannot be made any smaller since the two integers 500 and 91 have no common factors.
Signals will thus arrive at the phase detector at a rate of Fref/91, i.e., 27 MHz÷91, or about 296 KHZ. At this frequency the local oscillator will run for about 1/296 KHz, or about 3.4 microseconds (μS), before the phase can be adjusted. During this period between adjustments, differences may begin to accumulate in the phase of the signal from the local oscillator as compared to the input signal, and the system may exhibit a higher than desirable phase noise.
The generally accepted means to avoid low frequency signals being applied to the phase detector in such cases where M and N are largely relatively prime is known as the “variable modulus pre-scalar” solution. In such a solution, N is made to approximate a large value by spending various amounts of time at two other values on either side of N. For example, in the case above where M/N is desired to be 500/91, Ni may instead be set to 50 and the value of N changed so that the average value of N will be 9.1. Thus, N will be 9 for nine operations in a row, and then 10 for a single operation, so that the sequence of values of N will be 9,9,9,9,9,9,9,9,9,10. In this case the average value of N is in fact 9.1, and the PLL will, on average, settle down into a pattern where the frequency of Flo is 50/9.1, i.e., 500/91, times the frequency of FREF, as required.
The variable modulus pre-scalar is thus a viable solution in the sense that it may reduce phase noise by reducing the time between phase detector events, but it also suffers from a problem in that there is “dither” between the two values of N that are used to obtain the desired average value. The systematic error in the value of N will show up as “side tones,” i.e., spurious responses in the spectrum of the local oscillator and thus an output signal that includes frequencies other than the desired output frequency. Various techniques may be used to control this, for example “noise shaping” of the dither, but none of these techniques approach the more ideal case where N=1.
It is thus desirable to find a solution for the situation where the desired frequency requires a ratio that is largely relatively prime but which avoids the use of a variable modulus pre-scalar while preserving the ability to generate any arbitrarily accurate local oscillator frequency.